VHDL code for writing or reading RAM memory

Title: To Study RAM.

Aim: To design the VHDL code for writing or reading RAM memory.

  1. To study the VHDL programming language.
  2. To study the RAM and types.
  3. To draw the flow chart.
  4. To develop a VHDL code for eight bit counter.
Software & Hardware Requirement:
  1. Minimum Pentium 4, 512 MB RAM & 40 HDD.
  2. Xilinx software version 9.1v.
RAM Theory: Random access memory (RAM) is a form of computer data storage. Today, it takes the form of integrated circuits that allow stored data to be accessed in any order with a worst case performance of constant time. Strictly speaking, modern types of DRAM are therefore not random access, as data is read in bursts, although the name DRAM / RAM has stuck. However, many types of SRAM, ROM, OTP, and NOR flash are still random access even in a strict sense. RAM is often associated with volatile types of memory (such as DRAM memory modules), where its stored information is lost if the power is removed. Many other types of non-volatile memory are RAM as well, including most types of ROM and a type of flash memory called NOR-Flash.

RAM stands for Random Access Memory. This means Information can be retrieve and store by the computer at any order. RAM gives your computer a temporary place to process electronic data. This means that, RAM chips continue to store information only as long as computer has electrical power. In other words, when you shut off your computer, all the data stored in RAM are lost. All actual computing starts with the CPU (Central Processing Unit). The chipset supports the CPU and contains several controllers that control how information travels between the CPU and other components in the PC. The memory controller is part of the chipset and establishes the information flow between memory and the CPU.

Types of RAM:

1.      SRAM (Static RAM)

2.      DRA (Dynamic RAM)

3.      SDRAM (Static/Dynamic RAM)

The above figure (a) shows the block diagram of a static RAM with n address lines, on data lines and three control lines. This data lines are bidirectional in order to reduce the required numbers of pins and the package size of the memory chip. When reading from the RAM, the data lines are outputs. When writing to the RAM the data lines serve as input. The three control lines function as follows.

CS: When asserted low, chip select the memory chip so the memory read and write operations are possible.

OE: When asserted low, output enables he memory output onto an external bus.

WE: When asserted low, write enable allows data to be written to the RAM.

We say that a signal is asserted when it is in its active state. An active low signal is asserted when it is high. The truth table for the RAM describes its basic operations, high impedance Z in the I/O column means that the output buffers have high impedance Z and output and the data inputs are not used. In the read I/O lines after the memory access time, in the write mode input data is connected to the latch input in the selected memory cells. When WE is low but writing to the latches in the memory cells is not completed until either WE is goes high or the chip is deselected. The truth table does not take memory timing into account.

Result: The output waveform shows write as well as read operation by simple RAM design        


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