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Universal Shift Register using VHDL.

Shift_Registers

 

Title: To Study the Universal Shift Register.

Aim: To design Universal Shift Register using VHDL.

 

Objectives:

 

  1. To study the VHDL programming language.
  2. To study the Shift Register and types.
  3. To study Universal Shift Register
  4. To draw the flow chart.
  5. To develop a VHDL code for Universal Shift Register.

Software & Hardware Requirement:

  1. Minimum Pentium 4, 512 MB RAM & 40 HDD.
  2. Xilinx software version 9.1v.

 

Theory of Shift Register: In digital circuits, a shift register is a cascade of flip flops, sharing the same clock, which has the output of anyone but the last flip-flop connected to the “data” input of the next one in the chain, resulting in a circuit that shifts by one position the one-dimensional “bit array” stored in it, shifting in the data present at its input and shifting out the last bit in the array, when enabled to do so by a transition of the clock input. More generally, a shift register may be multidimensional; such that its “data in” input and stage outputs are themselves bit arrays: this is implemented simply by running several shift registers of the same bit-length in parallel.

Types of Shift Register:

  1. Serial-in, serial-out (SISO)

2.      Serial-in, parallel-out     (SIPO)

3.      Parallel-in, Serial-out     (PISO)

  1. Parallel-in, Parallel-out (PIPO)

Application of Shift Register:

  1. It is used for digital telephone.
  2. It is used in ring counter.

Designing: The function characteristics of the 74F194, 4-bit bidirectional shift register is shown in the function table. The register is fully synchronous with all operation taking place less than 9-ns for 74F, making the device especially useful for implementing very high speed CPU or memory for buffer register. The circuit provides parallel input and parallel output, right shift control input and direct clear line. In the parallel load mode, the unit function as a set of four D-flip flops. The two mode control bit s1 and s2 provides four mode of operation as follows.

Operation types:

  1. Shift Left Logic filled with zero (sll).
  2. Shift Right Logic filled with zero (srl).
  3. Rotate Left (rol).
  4. Rotate Right (ror).
  5. Shift Left Arithmetic filled with right bit(sla).
  6. Shift Right Arithmetic filled with left bit(sla).

Designing: Universal Shift Register: The functional characteristic of the 74F194, 4-bit bidirectional Shift register is fully synchronous with all operations taking place less than for 74F making the devices especially useful for implementing very high speed or memory for buffer registers. The ckt provides parallel input and parallel output right shift and left shift. Input operating mode, control input and a direct ordinary clear line. In the parallel load mode, the unit function as a set of four D-flip flops. The two mode control bits S1 and S2 provides four modes of operation as follows.

Mode Control  

Register Operation

S1 S0
0 0 Return the present state (No change )
0 1 Shift Right Cin the direction QA and QB
1 0 Shift left(In the direction Q and QB)
1 1 Parallel load D1,D2,D3,D4 into QA, QB,QC and QD

 

The shift and load operations occurs synchronously on the connected internally to all four flip flop.

Procedure:

  1. Design the universal shift register using VHDL. Declare the input and output of the circuit.
  2. Inputs Clk, S0,S1,S2 and data (in bit).
  3. The begin architecture section of your code here specially the actual functionality of your ckt. Then process the clk and clr.
  4. Then begin Asynchronous active low clear input. To write the all code.
  5. Synthesize the design using synthesis option from process window. Simulate the using launch Modulation Simulator.
  6. To verify the result.

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