Implementation of 4-bit wide 8:1 Multiplexer by using VHDL


Title: Implementation of 4-bit wide 8:1 Multiplexer by using VHDL

Aim:  To design and verify the truth table of a 4-bit wide 8:1 multiplexer.




  1. To study the VHDL programming language.
  2. To design 8:1 multiplexer using VHDL
  3. To develop a VHDL code for 4-bit wide 8:1 multiplexer
  4. To verify the truth table for 8;1 multiplexer.

 Software & Hardware Requirement:

  1. Minimum Pentium 4, 512 MB RAM & 40 HDD.
  2. Xilinx software version 9.1v

Theory Multiplexer: 8:1 MUX can be design using VHDL. A multiplexer is a combinational circuit that select binary information from one of many input lines and set of selection lines. There are 2n inputs lines and ‘n’ selection lines. Whose bit combination determine which inputs select. A multiplexer is also called as a data selecto, since it select one of many inputs and 8-binary inforamtion to the output lines. The size of multiplexer is specified by the number 2n of its data input lines and single output lines. The ‘n’ selection lines are implied from the 2n data lines.

Truth Table:

Select lines Output


S2 S1 S0
0 0 0 D0
0 0 1 D1
0 1 0 D2
0 1 1 D3
1 0 0 D4
1 0 1 D5
1 1 0 D6
1 1 1 D7


Test Procedure for 8:1 Multiplexer:

  • Design 8:1 multilplexer using K-map technique.
  • Enter the program for 8:1 multiplexer in the source window of the VHDL.
  • Synthesis the design using “Synthesis” option from process window.
  • After error free analysis simulate the design using process window.
  • To view the design using View RTL.
  • The waveform will appear for different input condition in the wave window from the simulation.
  • To verify the result and test the circuit.

Application of MUX:

  • It is used in Cable TV.
  • It is used in telephony.
  • It is used in multi user O.S.


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