Digital

Eight bit Counter and JK flip flop using VHDL

JK FF

Title: Practical Based on VHDL Programming (Sequential logic)

Aim: To design Eight bit Counter and JK flip flop using VHDL.

 

Objectives:

 

  1. To study the VHDL programming language.
  2. To study the Counter and types.
  3. To study the MUX.
  4. To develop a VHDL code for eight bit counter and master-slave J-K flip-flop.

Software & Hardware Requirement:

  1. Minimum Pentium 4, 512 MB RAM & 40 HDD.
  2. Xilinx software version 9.1v.

Counter Theory: In digital logic and computing, a counter is a device which stores (and sometimes displays) the number of times a particular event or process has occurred, often in relationship to a clock signal. A circuit used for counting the pulses is known as binary counter. Digital counter are often needed to count events. The counters are composed of flip flops. A circuit with ‘n’ flip flops has 2n possible states. An 8-bit counter to be counted are connected to the clock inputs of the first flip flops the output of first flip flop is connected as a clock input to the second flip flop. The flip flops are cleared by applying logic zero ‘0’ at the clear input by terminal. For normal counting is to be maintained as logic 1.

Types of Counter:

  1. Asynchronous (ripple) counter – changing state bits are used as clocks to subsequent state flip- flops
  2. Synchronous counter – all state bits change under control of a single clock
  3. Decade counter – counts through ten states per stage
  4. Up/down counter – counts both up and down, under command of a control input
  5. Ring counter – formed by a shift register with feedback connection in a ring
  6. Johnson counter – a twisted ring counter
  7. Cascaded counter.

Application: In computability theory, a counter is considered a type of memory. A counter stores a single natural number (initially zero) and can be arbitrarily many digits long. A counter is usually considered in conjunction with a finite-state machine (FSM), which can perform the following operations on the counter.

 

Theory Flip Flop: In electronics, a flip-flop or latch is a circuit that has two stable states and can be used to store state information. The circuit can be made to change state by signals applied to one or more control inputs and will have one or two outputs. It is the basic storage element in sequential logic. Flip-flops and latches are a fundamental building block of digital electronics systems used in computers, communications, and many other types of systems.

Flip-flops and latches are used as data storage elements. Such data storage can be used for storage of state, and such a circuit is described as sequential logic. When used in a finite-state machine, the output and next state depend not only on its current input, but also on its current state (and hence, previous inputs). It can also be used for counting of pulses, and for synchronizing variably-timed input signals to some reference timing signal.

Flip-flops can be either simple (transparent or opaque) or clocked (synchronous or edge-triggered); the simple ones are commonly called latches. The word latch is mainly used for storage elements, while clocked devices are described as flip-flops.

Types of Flip Flop: Flip-flops can be divided into common types: the SR (“set-reset”), D (“data” or “delay”, T (“toggle”), and JK types are the common ones. The behavior of a particular type can be described by what is termed the characteristic equation, which derives the “next” (i.e., after the next clock pulse) output, Qnext, in terms of the input signal(s) and/or the current output, Q.

  • SR Flip Flop
  • JK Flip Flop
  • D Flip Flop
  • T Flip Flop

Application of Flip Flop: Flip-flop is a basic memory circuit that is used for storing one-bit binary information. The flip-flops are used in:

  1. Bounce elimination switch
  2. Latch
  3. Register
  4. Counter
  5. Memory.

Test Procedure for 8-bit counter:

  • Enter the program for eight bit counter in the source window of VHDL.
  • Synthesize the design using Synthesis option from process window.
  • After error free analysis simulate the design using launch modelsim simulator.
  • See the schematic of the design by using view RTL schematic from the process window.
  • The input and output signal i.e. CLK, CLR, T,Q, will appear in the signal window select one input signal, declare a count signal in the architecture declaration and apply clock signal to the input.
  • Apply proper duty cycle and period for ‘CLK’ and apply force input to the T input. Simulate the design using “RUN ALL” submenu from the ‘RUN’ menu.
  • The waveform will appear for different input condition in wave window from the simulator.

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