8051 Core Specification


  • MCS-51 family, originally designed by Intel in the 1980’s
  • Used in a large percentage of embedded systems
  • Includes several on-chip peripherals, like timers and counters
  • 128 bytes of on-chip data memory and up to 4K bytes of on-chip program memory


  • 8-bit CPU optimized for control applications
  • Extensive Boolean processing (single-bit logic) capabilities
  • 64K Program Memory address space
  • 64K Data Memory address space
  • Up to 4K bytes of on-chip Program Memory
  • 128 bytes of on-chip Data RAM
  • 32 bi-directional and individually addressable I/O lines
  • Two 16-bit timer/counters
  • 6-source/5-vector interrupt structure with two priority levels


  • Memory Organization
  • CPU Clock
  • Interrupt Structure
  • Port Structures
  • Timer/Counters
  • Reset

Memory Organization

  • Logical separation of program and data memory
  • Separate address spaces for Program (ROM) and Data (RAM) Memory
  • Allow Data Memory to be accessed by 8-bit addresses quickly and manipulated by 8-bit CPU
  • Program Memory
  • Only be read, not written to
  • The address space is 16-bit, so maximum of 64K bytes
  • Up to 4K bytes can be on-chip (internal) of 8051 core
  • PSEN (Program Store Enable) is used for access to external Program Memory
  • Data Memory
  • Includes 128 bytes of on-chip Data Memory which are more easily accessible directly by its instructions
  • There is also a number of Special Function Registers (SFRs)
  • Internal Data Memory contains four banks of eight registers and a special 32-byte long segment which is bit addressable by 8051 bit-instructions
  • External memory of maximum 64K bytes is accessible by “movx”

CPU Clock

8051 microcontroller has a clock input pin

Interrupt Structure

  • The 8051 provides 4 interrupt sources
  • Two external interrupts
  • Two timer interrupts
  • Additional description follows in Operations chapter

Port Structures 

  • The 8051 contains four I/O ports
  • All four ports are bidirectional
  • Each port has SFR (Special Function Registers P0 through P3) which works like a latch, an output driver and an input buffer
  • Both output driver and input buffer of Port 0 and output driver of Port 2 are used for accessing external memory
  • Accessing external memory works like this
  • Port 0 outputs the low byte of external memory address (which is time-multiplexed with the byte being written or read)
  • Port 2 outputs the high byte (only needed when the address is 16 bits wide)
  • Port 3 pins are multifunctional
  • The alternate functions are activated with the 1 written in the corresponding bit in the port SFR

Read-Modify-Write Feature

When reading a port some instructions read the latch and others read the pin

The instructions that read the latch rather than the pin are the ones that read a value (possibly change it), an then rewrite it to the latch are called “read-modify-write” instructions


The 8051 has two 16-bit Timer/Counter registers

  1. Timer 0
  2. Timer 1

Both can work either as timers or event counters

Both have four different operating modes from which to select (all modes are described in Operations chapter)


The reset input is the RST pin


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